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DTSTART:20171029T030000
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UID:calendar.13025.field_data.0@www.glad.uniroma1.it
DTSTAMP:20260404T211114Z
CREATED:20180301T084155Z
DESCRIPTION:In the last years the traditional ways to keep the increase of 
 hardware performance to the rate predicted by the Moore's Law vanished. Wh
 en uni-cores were the norm\, hardware design was decoupled from the softwa
 re stack thanks to a well defined Instruction Set Architecture (ISA). This
  simple interface allowed developing applications without worrying too muc
 h about the underlying hardware\, while computer architects proposed techn
 iques to aggressively exploit Instruction-Level Parallelism (ILP) in super
 scalar processors. Current multi-cores are designed as simple symmetric mu
 ltiprocessors on a chip. While these designs are able to compensate the cl
 ock frequency stagnation\, they face multiple problems in terms of power c
 onsumption\, programmability\, resilience or memory. The solution is to gi
 ve more responsibility to the runtime system and to let it tightly collabo
 rate with the hardware. The runtime has to drive the design of future mult
 i-cores architectures.  In this talk\, we introduce an approach towards a 
 Runtime-Aware Architecture (RAA)\, a massively parallel architecture desig
 ned from the runtime's perspective. RAA aims at supporting the activity of
  the parallel runtime system in three ways: First\, to enable fine-grain t
 asking and support the opportunities it offers\; second\, to improve the p
 erformance of the memory subsystem by exposing hybrid hierarchies to the r
 untime system and\, third\, to improve performance by using vector units. 
 During the talk\, we will give a general overview of the problems RAA aims
  to solve and provide some examples of hardware components supporting the 
 activity of the runtime system in the context of multi-core chips.  Short 
 bio:Mateo Valero CortesDirector of the Barcelona Supercomputing CenterProf
 essor\, University of Catalonia (UPC)Barcelona\, SpainMateo Valero\, http:
 //www.bsc.es/cv-mateo/\, obtained his Telecommunication Engineering Degree
  from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Te
 lecommunications from the Technical University of Catalonia (UPC) in 1980.
  He is a professor in the Computer Architecture Department at UPC\, in Bar
 celona. His research interests focuses on high performance architectures. 
 He has published approximately 700 papers\, has served in the organization
  of more than 300 International Conferences and he has given more than 500
  invited talks. He is the director of the Barcelona Supercomputing Centre\
 , the National Centre of Supercomputing in Spain. Dr. Valero has been hono
 ured with several awards. Among them\, the Eckert-Mauchly Award 2007 by th
 e IEEE and ACM\; Seymour Cray Award 2015 by IEEE\; Charles Babbage 2017 by
  IEEE\; Harry Goode Award 2009 by IEEE: ACM Distinguished Service Award 20
 12\; Euro-Par Achievement Award 2015\; the Spanish National Julio Rey Past
 or award\, in recognition of research in Mathematics\; the Spanish Nationa
 l Award “Leonardo Torres Quevedo” that recognizes research in engineering\
 ;  the “King Jaime I” in basic research given by Generalitat Valenciana\; 
 the  Research Award by the Catalan Foundation for Research and Innovation 
 and the “Aragón Award” 2008  given by the Government of Aragón. He has bee
 n named Honorary Doctor by the University of Chalmers\, by the University 
 of Belgrade\, by the Universities of Las Palmas de Gran Canaria\, Zaragoza
 \, Complutense de Madrid\, Cantabria and Granada in Spain\, by the Univers
 ity of Veracruz  and CINVESTAV in Mexico.  'Hall of the Fame' member of th
 e ICT European Program (selected as one of the 25 most influents European 
 researchers in IT during the period 1983-2008. Lyon\,November 2008)\; Hono
 ured with Creu de Sant Jordi 2016 by Generalitat de Catalunya. It is the h
 ighest recognition granted by the Government. In December 1994\, Professor
  Valero became a founding member of the Royal Spanish Academy of Engineeri
 ng. In 2005 he was elected Correspondant Academic of the Spanish Royal Aca
 demy of Science\, in 2006  member of the Royal Spanish Academy of Doctors\
 , in 2008 member of the Academia Europaea and in 2012 Correspondant Academ
 ic of the Mexican Academy of Sciences. He is a Fellow of the IEEE\, Fellow
  of the ACM and an Intel Distinguished Research Fellow.  In 1998 he won a 
 “Favourite Son” Award of his home town\, Alfamén (Zaragoza) and in 2006\, 
 his native town of Alfamén named their Public College after him.
DTSTART;TZID=Europe/Paris:20180525T090000
DTEND;TZID=Europe/Paris:20180525T090000
LAST-MODIFIED:20191008T082902Z
LOCATION:Aula Magna
SUMMARY:Runtime Aware Architectures - Mateo Valero\, University of Cataloni
 a (UPC)
URL;TYPE=URI:http://www.glad.uniroma1.it/node/13025
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